搜索资源列表
5_lined_cpu
- 简单5级流水线CPU的verilog逻辑设计-Simple line 5 of the CPU logic design verilog
111m
- verilog code for cpu and bus.
CPU_verilog
- 一个4级流水线CPU的verilog代码，供参考学习使用，有些语句不能综合，可以通过它学习CPU的工作原理。-A 4-stage pipeline CPU' s verilog code, learning to use for reference, some statements can not be integrated, you can learn from CPU through its works.
CPU_code
- 基本的cpu verilog code 可用來瞭解基本cpu運作-Basic cpu verilog code can be used to understand the operation of the basic cpu
cpu16
- Verilog下描述16位CPU，虽然有点简单，但具有一定的可读性，内附夏宇闻老师的8位CPU文档-Verilog descr iption of 16-bit CPU, though a bit simple, but with a certain degree of readability, XIA Yu-Wen teachers containing 8-bit CPU Documentation
Chapter1-5
- 第一章到第五章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例
16_bits_CPU_verilog_code
- 利用Verilog设计的16位CPU的设计案例-the example of 16 bits CPU using verilog
RISCCPU
- 简单的CPU设计流程PPT，用于教学目的，可综合的verilog HDL设计。-A simple CPU design process PPT, for teaching purposes, can be integrated verilog HDL design.
W5300_Driver_V1[1].1.1
- 硬件TCPIP协议栈芯片W5300的使用例子代码,该芯片内部通过硬件实现了TCPIP协议栈,可减少CPU运行协议栈的开销.-Hardware TCPIP protocol stack chips W5300 examples of the use of code, the chip hardware implementation of the internal adoption of the TCPIP protocol stack can reduce the CPU overhead of
utopia
- utopia，system verilog写的CPU测试平台代码-utopia, system verilog code written in CPU test platform
SinglecycleCPU
- 用Verilog实现一个简单的单周期CPU，并运行Quicksort程序以验证正确性。-This file is written in Verilog to achieve a single cycle processor. It can run in Quartus2.
_8259A
- 8259A是专门为了对8085A和8086/8088进行中断控制而设计的芯片，它是可以用程序控制的中断控制器。单个的8259A能管理8级向量优先级中断。在不增加其他电路的情况下，最多可以级联成64级的向量优先级中断系统。8259A有多种工作方式，能用于各种系统。各种工作方式的设定是在初始化时通过软件进行的。 在总线控制器的控制下,8259A芯片可以处于编程状态和操作状态.编程状态是CPU使用IN或OUT指令对8259A芯片进行初始化编程的状态- 8259A is designed t
LCD12864_ST7920
- LCD12864驱动程序 可实现以ARM为CPU的LCD12864的驱动-LCD12864 driver enables ARM-CPU of LCD12864 drive
risc8
- verilog risc8 cpu-verilog risc8 cpu
i2c
- I2C verilog代码，支持master和slave方式，内置CPU接口-I2C verilog RTL code， support master and slave mode
alu
- this is source code in verilog for arithmatic logic unit for RISC cpu
RISCcpu
- this verilog model of RISC CPU-this is verilog model of RISC CPU
F10-Single-Cycle-MIPS
- This a verilog code of single cycle mips-This is a verilog code of single cycle mips
CPU
- 多周期CPU设计，使用Verilog HDL语言编程，实现MIPS的指令系统。-CPU design with verilog hdl language.Instructions from MIPS.Something in detial is not perfect.
cpu
- 简单的cpu，以verilog语言写的，希望大家能提点意见。-Simple cpu, the verilog language to write, and I hope we can Tidianyijian.